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Power control (PWR)
5.5.16
PWR port H pull-down control register (PWR_PDCRH)
This register is not reset when exiting Standby modes and with PWRRST bit in the
RCC_APB1RSTR1 register.
Access: additional APB cycles are needed to access this register versus those needed for a
standard APB access (three for a write and two for a read).
Address offset: 0x05C
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:4 Reserved, must be kept at reset value.
Bit 3 PD3: Port PH[3] pull-down
When set, this bit activates the pull-down on PH[3] when both APC bits are set in
control register 3
Bits 2:0 Reserved, must be kept at reset value.
5.5.17
PWR extended status and status clear register (PWR_EXTSCR)
Access: three additional APB cycles are needed to write this register versus a standard APB
write.
Address offset: 0x088
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
C1DS
Res.
Res.
r
Bits 31:15 Reserved, must be kept at reset value.
Bit 14 C1DS: CPU Deep-Sleep mode
This bit is set by hardware when CPU enters Deep-Sleep mode.
0: CPU is running or in sleep
1: CPU is in Deep-Sleep
Bits 13:11 Reserved, must be kept at reset value.
226/1306
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
(PWR_CR3).
28
27
26
25
Res.
Res.
Res.
12
11
10
9
C1STO
C1STO
Res.
PF
P2F
r
r
24
23
22
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
24
23
22
Res.
Res.
Res.
8
7
6
C1SBF
Res.
Res.
r
RM0461 Rev 5
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
Res.
Res.
PD3
Res.
rw
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
Res.
Res.
Res.
Res.
RM0461
17
16
Res.
Res.
1
0
Res.
Res.
PWR
17
16
Res.
Res.
1
0
C1CSS
Res.
F
w
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