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RM0461
26.7.10
LPTIM2 option register (LPTIM2_OR)
Address offset: 0x020
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:2 Reserved, must be kept at reset value.
Bits 1:0 OR_[1:0]:
00: input 1 is connected to I/O
01: input 1 is connected to COMP1_OUT
10: input 1 is connected to COMP2_OUT
11: input 1 is connected to COMP1_OUT OR COMP2_OUT
26.7.11
LPTIM3 option register (LPTIM3_OR)
Address offset: 0x020
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:2 Reserved, must be kept at reset value.
Bits 1:0 OR_[1:0]:
00: input 1 is connected to I/O
01: input 1 is connected to COMP1_OUT
10: input 1 is connected to COMP2_OUT
11: input 1 is connected to COMP1_OUT OR COMP2_OUT
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
24
23
22
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
24
23
22
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
RM0461 Rev 5
Low-power timer (LPTIM)
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
Res.
Res.
Res.
Res.
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
Res.
Res.
Res.
Res.
17
16
Res.
Res.
1
0
OR_1
OR_0
rw
rw
17
16
Res.
Res.
1
0
OR_1
OR_0
rw
rw
867/1306
870
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