STMicroelectronics STM32WLEx Reference Manual page 254

Reset and clock control (RCC)
Bits 7:0 MSICAL[7:0]: MSI clock calibration
These bits are initialized at startup with the factory-programmed MSI calibration trim value.
When MSITRIM is written, MSICAL is updated with the sum of MSITRIM and the factory trim
value.
Note: Adding a MSITRIM value with the MSB set results in a subtraction.
6.4.3 RCC clock configuration register (RCC_CFGR)
Address offset: 0x008
Reset value: 0x0007 0000
(after POR reset and after wakeup from Standby)
Access: 0 ≤ wait state ≤ 2, word, half-word and byte access
One or two wait states inserted only if the access occurs during clock source switch.
From 0 to 15 wait states inserted if the access occurs when the APB or AHB prescalers
values update is ongoing.
31 30 29
Res. MCOPRE[2:0]
rw rw
15 14 13
STOP
Res. PPRE2[2:0]
WUCK
rw rw
Bit 31 Reserved, must be kept at reset value.
Bits 30:28 MCOPRE[2:0]: Microcontroller clock output prescaler
254/1306
28 27 26 25
MCOSEL[3:0]
rw rw rw rw
12 11 10 9
PPRE1[2:0]
rw rw rw rw
These bits are set and cleared by software.
It is highly recommended to change this prescaler before MCO output is enabled.
000: MCO divided by 1
001: MCO divided by 2
010: MCO divided by 4
011: MCO divided by 8
100: MCO divided by 16
Others: not allowed
24 23 22
Res. Res.
rw
8 7 6
HPRE[3:0]
rw rw rw
RM0461 Rev 5
21 20 19 18
PPRE
Res. Res. Res.
2F
r
5 4 3 2
SWS[1:0]
rw rw r r
RM0461
17 16
PPRE
HPREF
1F
r r
1 0
SW[1:0]
rw rw