Table 187. Prescaler Division Ratios; Figure 249. Glitch Filter Timing Diagram - STMicroelectronics STM32WLEx Reference Manual

RM0461
The digital filters are divided into two groups:
•
The first group of digital filters protects the LPTIM internal or external inputs. The digital
filters sensitivity is controlled by the CKFLT bits
•
The second group of digital filters protects the LPTIM internal or external trigger inputs.
The digital filters sensitivity is controlled by the TRGFLT bits.
Note: The digital filters sensitivity is controlled by groups. It is not possible to configure each digital
filter sensitivity separately inside the same group.
The filter sensitivity acts on the number of consecutive equal samples that should be
detected on one of the LPTIM inputs to consider a signal level change as a valid transition.
Figure 249
programmed.
CLKMUX
Input
Filter out
Note: In case no internal clock signal is provided, the digital filter must be deactivated by setting
the CKFLT and TRGFLT bits to '0'. In that case, an external analog filter may be used to
protect the LPTIM external inputs against glitches.
26.4.6 Prescaler
The LPTIM 16-bit counter is preceded by a configurable power-of-2 prescaler. The prescaler
division ratio is controlled by the PRESC[2:0] 3-bit field. The table below lists all the possible
division ratios:
shows an example of glitch filter behavior in case of a 2 consecutive samples

Figure 249. Glitch filter timing diagram

2 consecutive samples

Table 187. Prescaler division ratios

programming
000
001
010
011
100
101
110
111
RM0461 Rev 5
2 consecutive samples
dividing factor
Low-power timer (LPTIM)
Filtered
MS32490V1
/1
/2
/4
/8
/16
/32
/64
/128
847/1306
870