STMicroelectronics STM32WLEx Reference Manual page 50

List of figures RM0461
Figure 153. 3-phase combined PWM signals with multiple trigger pulses per period . . . . . . . . . . . . . 653
Figure 154. Complementary output with dead-time insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654
Figure 155. Dead-time waveforms with delay greater than the negative pulse . . . . . . . . . . . . . . . . . . 654
Figure 156. Dead-time waveforms with delay greater than the positive pulse. . . . . . . . . . . . . . . . . . . 655
Figure 157. Break and Break2 circuitry overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657
Figure 158. Various output behavior in response to a break event on BRK (OSSI = 1) . . . . . . . . . . . 659
Figure 159. PWM output state following BRK and BRK2 pins assertion (OSSI=1) . . . . . . . . . . . . . . . 660
Figure 160. PWM output state following BRK assertion (OSSI=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . 661
Figure 161. Output redirection (BRK2 request not represented) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 662
Figure 162. Clearing TIMx OCxREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 663
Figure 163. 6-step generation, COM example (OSSR=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664
Figure 164. Example of one pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 665
Figure 165. Retriggerable one pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667
Figure 166. Example of counter operation in encoder interface mode. . . . . . . . . . . . . . . . . . . . . . . . . 668
Figure 167. Example of encoder interface mode with TI1FP1 polarity inverted. . . . . . . . . . . . . . . . . . 669
Figure 168. Measuring time interval between edges on 3 signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 670
Figure 169. Example of Hall sensor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672
Figure 170. Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673
Figure 171. Control circuit in Gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 674
Figure 172. Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675
Figure 173. Control circuit in external clock mode 2 + trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . 676
Figure 174. General-purpose timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720
Figure 175. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 722
Figure 176. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 722
Figure 177. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723
Figure 178. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 724
Figure 179. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 724
Figure 180. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 725
Figure 181. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded). . . . . 725
Figure 182. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded). . . . . . . . 726
Figure 183. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 727
Figure 184. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 727
Figure 185. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 728
Figure 186. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 728
Figure 187. Counter timing diagram, Update event when repetition counter
is not used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 729
Figure 188. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . . . . . . . . . . . . 730
Figure 189. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 731
Figure 190. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . . . . . . . . . . . 731
Figure 191. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 732
Figure 192. Counter timing diagram, Update event with ARPE=1 (counter underflow). . . . . . . . . . . . 732
Figure 193. Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . . . . . . . . . . 733
Figure 194. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 734
Figure 195. TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 734
Figure 196. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 735
Figure 197. External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 736
Figure 198. Control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 737
Figure 199. Capture/Compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . 737
Figure 200. Capture/Compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 738
Figure 201. Output stage of Capture/Compare channel (channel 1) . . . . . . . . . . . . . . . . . . . . . . . . . . 738
Figure 202. PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 740
Figure 203. Output compare mode, toggle on OC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742
50/1306 RM0461 Rev 5