RM0461
Bits 31:23 Reserved, must be kept at reset value.
Bits 22:16 WRP1B_END[6:0]: WRP area B end offset
Bits 15:7 Reserved, must be kept at reset value.
Bits 6:0 WRP1B_STRT[6:0]: WRP area B start offset
3.8.12
FLASH PCROP zone B start address register
(FLASH_PCROP1BSR)
Address offset: 0x034
Reset value: 0xFFFF FFFF
Default reset value from ST production is given. Subsequently, 0b1111 1111 1111 1111 1111
1111 XXXX XXXX, the option bits are loaded with user values from the flash memory at
reset release.
Access: no wait state when no flash memory operation is ongoing. Word and half-word
access.
This register can only be written by the CPU in RDP level 0 or RDP level 1.
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 PCROP1B_STRT[7:0]: PCROP1B area start offset
3.8.13
FLASH PCROP zone B end address register
(FLASH_PCROP1BER)
Address offset: 0x038
Reset value: 0xFFFF FF00
Default reset value from ST production is given. Subsequently, 0b1111 1111 1111 1111 1111
1111 XXXX XXXX, the option bits are loaded with user values from the flash memory at
reset release.
Access: no wait state when no flash memory operation is ongoing. Word and half-word
access.
This register can only be written by the CPU in RDP level 0 or RDP level 1.
WRPB1_END contains the last 2-Kbyte page of the WRP area B.
WRPB1_END contains the first 2-Kbyte page of the WRP area B.
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
Contains the first 1-Kbyte page of the PCROP1B area.
24
23
22
Res.
Res.
Res.
Res.
8
7
6
Res.
rw
rw
RM0461 Rev 5
Embedded flash memory (FLASH)
21
20
19
18
Res.
Res.
Res.
5
4
3
2
PCROP1B_STRT[7:0]
rw
rw
rw
rw
17
16
Res.
Res.
1
0
rw
rw
105/1306
108
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