STMicroelectronics STM32WLEx Reference Manual page 272

Reset and clock control (RCC)
6.4.17 RCC AHB3 peripheral clock enable register (RCC_AHB3ENR)
Address offset: 0x050
Reset value: 0x0208 0000
Access: no wait state, word, half-word and byte access
Note: When the peripheral clock is not active, the peripheral registers read or write access is not
supported.
31 30 29
Res. Res. Res.
15 14 13
Res. Res. Res.
Bits 31:26 Reserved, must be kept at reset value.
Bit 25 FLASHEN: Flash memory interface clock enable
Bits 24:20 Reserved, must be kept at reset value.
Bit 19 HSEMEN: HSEM clock enable
Bit 18 RNGEN: true RNG clocks enable
Bit 17 AESEN: AES accelerator clock enable
Bit 16 PKAEN: PKA accelerator clock enable
Bits 15:0 Reserved, must be kept at reset value.
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28 27 26 25
FLASH
Res. Res. Res.
EN
rw
12 11 10 9
Res. Res. Res. Res.
This bit can only be cleared when the Flash memory is in power down. Set and cleared by
software.
0: Flash interface clock disabled
1: Flash interface clock enabled
This bit is set and cleared by software.
0: HSEM clock disabled
1: HSEM clock enabled
This bit is set and cleared by software.
0: True RNG bus and kernel clocks disabled
1: True RNG bus and kernel clocks enabled
This bit is set and cleared by software.
0: AES clock disabled
1: AES clock enabled
This bit is set and cleared by software.
PKA clock is enabled when a hardware PKA SRAM erase is ongoing.
0: PKA clock disabled
1: PKA clock enabled
24 23 22
Res. Res. Res.
8 7 6
Res. Res. Res.
RM0461 Rev 5
21 20 19 18
HSEM RNG
Res. Res.
EN EN
rw rw
5 4 3 2
Res. Res. Res. Res.
RM0461
17 16
AES PKA
EN EN
rw rw
1 0
Res. Res.