STMicroelectronics STM32WLEx Reference Manual page 540

True random number generator (RNG)
Bit 5 CED: Clock error detection
Bit 4 Reserved, must be kept at reset value.
Bit 3 IE: Interrupt Enable
Bit 2 RNGEN: True random number generator enable
Bits 1:0 Reserved, must be kept at reset value.
540/1306
0: Clock error detection is enable
1: Clock error detection is disable
The clock error detection cannot be enabled nor disabled on-the-fly when the RNG is
enabled, that is to enable or disable CED the RNG must be disabled.
Writing this bit is taken into account only if CONDRST bit is set to 1 in the same access,
while CONFIGLOCK remains at 0. Writing to this bit is ignored if CONFIGLOCK = 1.
0: RNG Interrupt is disabled
1: RNG Interrupt is enabled. An interrupt is pending as soon as DRDY = 1, SEIS = 1 or
CEIS = 1 in the RNG_SR register.
0: True random number generator is disabled. Analog noise sources are powered off and
logic clocked by the RNG clock is gated.
1: True random number generator is enabled.
RM0461 Rev 5
RM0461