Figure 267. Data Transmission - STMicroelectronics STM32WLEx Reference Manual

Inter-integrated circuit (I2C) interface
Transmission
If the I2C_TXDR register is not empty (TXE=0), its content is copied into the shift register
after the ninth SCL pulse (the Acknowledge pulse). Then the shift register content is shifted
out on SDA line. If TXE = 1, meaning that no data is written yet in I2C_TXDR, SCL line is
stretched low until I2C_TXDR is written. The stretch is done after the ninth SCL pulse.
Shift register
I2C_TXDR
Hardware transfer management
The I2C has a byte counter embedded in hardware in order to manage byte transfer and to
close the communication in various modes such as:
–
–
–
The byte counter is always used in master mode. By default it is disabled in slave mode, but
it can be enabled by software by setting the SBC (slave byte control) bit in the I2C_CR1
register.
The number of bytes to be transferred is programmed in the NBYTES[7:0] bit field in the
I2C_CR2 register. If the number of bytes to be transferred (NBYTES) is greater than 255, or
if a receiver wants to control the acknowledge value of a received data byte, the reload
mode must be selected by setting the RELOAD bit in the I2C_CR2 register. In this mode,
the TCR flag is set when the number of bytes programmed in NBYTES is transferred, and
an interrupt is generated if TCIE is set. SCL is stretched as long as TCR flag is set. TCR is
cleared by software when NBYTES is written to a non-zero value.
When the NBYTES counter is reloaded with the last number of bytes, RELOAD bit must be
cleared.
958/1306

Figure 267. Data transmission

ACK pulse
SCL
xx
TXE
data0
NACK, STOP and ReSTART generation in master mode
ACK control in slave receiver mode
PEC generation/checking when SMBus feature is supported
xx
wr data1 wr data2
data1
RM0461 Rev 5
ACK pulse
xx
data2
RM0461
legend:
SCL
stretch
MS19849V1