Extended interrupts and event controller (EXTI)
The CPU event must be unmasked in EXTI_EMR to generate an event. When the enabled
edges occur on the event input, a CPU event pulse is generated. There is no event pending
bit.
For the configurable event inputs, an event request can be generated by software, setting to
1 the corresponding bit in the interrupt/event register EXTI_SWIER. This allows the
generation of a rising edge on the event. The edge event pending bit must be set in
EXTI_PR, irrespective of the setting in EXTI_RTSR.
14.6
EXTI registers
The EXTI register map is divided in sections listed in the table below.
0x000 - 0x01C
0x020 - 0x03C
0x080 - 0x0BC
All these registers can be accessed with word (32-bit), half-word (16-bit) and byte (8-bit)
access.
14.6.1
EXTI rising trigger selection register (EXTI_RTSR1)
Address offset: 0x000
Reset value: 0x0000 0000
Contains only register bits for configurable events.
31
30
29
Res.
Res.
Res.
Res.
15
14
13
RT15
RT14
RT13
RT12
rw
rw
rw
Bits 31:23 Reserved, must be kept at reset value.
Bit 22 RT22: rising trigger event configuration bit of configurable event input 22
Note: The configurable event inputs are edge triggered. No glitch must be generated on
Bit 21 RT21: rising trigger event configuration bit of configurable event input 21
Bits 20:17 Reserved, must be kept at reset value.
410/1306
Table 84. EXTI register map sections
Address
General configurable event [31:0] configuration
General configurable event [63:32] configuration
CPU input event configuration
28
27
26
25
Res.
Res.
Res.
12
11
10
9
RT11
RT10
RT9
rw
rw
rw
rw
0: Rising trigger disabled (for event and interrupt) for input line
1: Rising trigger enabled (for event and interrupt) for input line
these inputs. If a rising edge on the configurable event input occurs while writing to the
register, the associated pending bit is not set.
Rising and falling edge triggers can be set for the same configurable event input. In this
case, both edges generate a trigger.
Description
24
23
22
Res.
Res.
RT22
RT21
rw
8
7
6
RT8
RT7
RT6
rw
rw
rw
RM0461 Rev 5
21
20
19
18
Res.
Res.
Res.
rw
5
4
3
2
RT5
RT4
RT3
RT2
rw
rw
rw
rw
RM0461
17
16
Res.
RT16
rw
1
0
RT1
RT0
rw
rw
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