Inter-integrated circuit (I2C) interface
user can disable this analog filter by setting the ANFOFF bit, and/or select a digital filter by
configuring the DNF[3:0] bit in the I2C_CR1 register.
When the digital filter is enabled, the level of the SCL or the SDA line is internally changed
only if it remains stable for more than DNF x I2CCLK periods. This allows spikes with a
programmable length of 1 to 15 I2CCLK periods to be suppressed.
Pulse width of
suppressed spikes
Benefits
Drawbacks
Caution:
Changing the filter configuration is not allowed when the I2C is enabled.
952/1306
Table 213. Comparison of analog vs. digital filters
-
Analog filter
≥ 50 ns
Available in Stop mode
Variation vs. temperature,
voltage, process
Programmable length from 1 to 15 I2C peripheral
clocks
– Programmable length: extra filtering capability
versus standard requirements
– Stable length
Wakeup from Stop mode on address match is not
available when digital filter is enabled
RM0461 Rev 5
RM0461
Digital filter
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