Flash Option Bytes; Option Bytes Description - STMicroelectronics STM32WLEx Reference Manual

Embedded flash memory (FLASH)
Programming errors causing a bus error
The error conditions listed below do not generate an error flag but a bus error instead:
•
AHB write to any page when RDP level 1 and boot is performed from the system flash
memory or SRAM1
•
AHB write when the flash memory is powered down
•
Read or write from the flash memory through the debugger
•
Read from the flash memory when fast row programming is ongoing, for the source
which requested the fast row programming
•
New programming request when the previous one is not finished
• FLASH_CR register write between the two accesses of a double-word programming
•
FLASH_CR register write when PESD is active (set)
• Write a wrong key in FLASH_KEYR or FLASH_OPTKEYR register
•
Any subsequent write to FLASH_KEYR or FLASH_OPTKEYR after unlocking the
respective feature
Programming and caches
If a flash memory write access impacts data in the data cache, the flash memory write
access modifies the data in the memory and in the cache.
If an erase operation in the flash memory also concerns data in the data cache or instruction
cache, the user must ensure that these data are rewritten before they are accessed during
code execution. Upon an erase operation, the cache content is invalidated.
Note: The ICache and DCache must be flushed only when disabled (ICEN or DCEN = 0).
3.4

FLASH option bytes

3.4.1

Option bytes description

The option bytes can be read from the memory locations listed in the table below or from the
following option byte registers:
•
FLASH option register (FLASH_OPTR)
•
FLASH PCROP zone A start address register (FLASH_PCROP1ASR)
•
FLASH PCROP zone A end address register (FLASH_PCROP1AER)
•
FLASH PCROP zone B start address register (FLASH_PCROP1BSR)
•
FLASH PCROP zone B end address register (FLASH_PCROP1BER)
•
FLASH WRP area A address register (FLASH_WRP1AR)
•
FLASH WRP area B address register (FLASH_WRP1BR)
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