Sub-Ghz Radio Generic Cfo Lsb Register (Subghz_Gcforl); Sub-Ghz Radio Generic Packet Control 1 Register; (Subghz_Gpktctl1R); Sub-Ghz Radio Generic Packet Control 1A Register - STMicroelectronics STM32WLEx Reference Manual

Sub-GHz radio (SUBGHZ)
Bits 7:4 Reserved, must be kept at reset value.
Bits 3:0 DEMOD_CFO[3:0]: actual frequency error from normalized value (MSB bits)
4.10.9

Sub-GHz radio generic CFO LSB register (SUBGHZ_GCFORL)

Address offset: 0x6B1
Reset value: 0x00
7 6
r r
Bits 7:0 DEMOD_CFO[7:0]: actual frequency error from normalized value (LSB bits)
4.10.10

Sub-GHz radio generic packet control 1 register

(SUBGHZ_GPKTCTL1R)

Address offset: 0x06B4
Reset value: 0x04
This register must be cleared to 0x00 when using packet types other than LoRa.
7 6
Res Res
Bits 7:3 Reserved, must be kept at reset value.
Bit 2 PBDETON: Preamble detection enable
Bits 1:0 PBDETLEN: Receiver preamble detection length
4.10.11

Sub-GHz radio generic packet control 1A register

(SUBGHZ_GPKTCTL1AR)

Address offset: 0x6B8
Reset value: 0x21
7 6
Res. Res.
Bits 7:6 Reserved, must be kept at reset value.
Bit 5 SYNCDETEN: Generic packet synchronization word detection enable
164/1306
5
r
5
Res
0b00: 8-bit preamble detection
0b01: 16-bit preamble detection
0b10: 24-bit preamble detection
0b11: 32-bit preamble detection
5
SYNCDETEN CONTTX
rw
4 3
DEMOD_CFO[7:0]
r r
4 3
Res Res
4 3
INFSEQSEL[1:0]
rw rw
RM0461 Rev 5
2 1
r r
2 1
PBDETON PBDETLEN[1:0]
rw rw
2 1
INFSQEQEN
rw rw
RM0461
0
r
0
rw
0
WHITEINI[8]
rw