Flash Pcrop Zone A End Address Register (Flash_Pcrop1Aer) - STMicroelectronics STM32WLEx Reference Manual

RM0461
3.8.9 FLASH PCROP zone A end address register
(FLASH_PCROP1AER)
Address offset: 0x028
Reset value: 0xFFFF FF00
Default reset value from ST production is given. Subsequently, 0bX111 1111 1111 1111 1111
1111 XXXX XXXX, the option bits are loaded with user values from flash memory at reset
release.
Access: no wait state when no flash memory operation is ongoing. Word, half-word access.
PCROP_RDP bit can be accessed with byte access
This register can only be written by the CPU in RDP level 0 or RDP level 1.
31 30 29
Res. Res. Res.
rs
15 14 13
Res. Res. Res. Res.
Bit 31 PCROP_RDP: PCROP area preserved when RDP level decreased
Bits 30:8 Reserved, must be kept at reset value.
Bits 7:0 PCROP1A_END[7:0]: PCROP1A area end offset
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
This bit is set only. It is reset after a full mass erase due to a change of RDP from level 1 to
level 0.
0: PCROP area not erased when the RDP level is decreased from level 1 to level 0
1: PCROP area erased when the RDP level is decreased from level 1 to level 0 (full mass
erase)
PCROP1A_END contains the last 1-Kbyte page of the PCROP1A area.
24 23 22
Res. Res. Res.
8 7 6
Res.
rw rw
RM0461 Rev 5
Embedded flash memory (FLASH)
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
PCROP1A_END[7:0]
rw rw rw rw
17 16
Res. Res.
1 0
rw rw
103/1306
108