Figure 178. Counter Timing Diagram, Internal Clock Divided By 2; Figure 179. Counter Timing Diagram, Internal Clock Divided By 4 - STMicroelectronics STM32WLEx Reference Manual

Advanced arm-based 32-bit mcus with sub-ghz radio solution
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General-purpose timer (TIM2)
Timerclock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag
Timerclock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag
724/1306

Figure 178. Counter timing diagram, internal clock divided by 2

CK_PSC
CNT_EN
0034
(UIF)

Figure 179. Counter timing diagram, internal clock divided by 4

CK_PSC
CNT_EN
0035
(UIF)
RM0461 Rev 5
0035
0036
0000
0036
RM0461
0001
0002
0003
MS31079V2
0000
0001
MS31080V2

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