Table 50. Clock Source Frequency - STMicroelectronics STM32WLEx Reference Manual

Reset and clock control (RCC)
6.2.9 Clock source frequency versus voltage scaling
The following table gives the different clock source frequencies depending on the product
voltage range.
Product voltage
range
Range 1
Range 2
1. The HSEPRE must be set to divide by two.
6.2.10 Clock security system on HSE32 (CSS)
The clock security system can be activated by software. In this case, the clock detector is
enabled after the HSE32 oscillator startup delay, and disabled when this oscillator is
stopped.
If a failure is detected on the HSE32 clock, the HSE32 oscillator is automatically disabled. A
clock failure event is sent to the break input of the advanced-control timers (TIM1 and
TIM16/17) and a HSE32 CSS interrupt is generated to inform the software about the failure,
allowing the MCU to perform rescue operations. The HSE32 CSS interrupt is linked to the
CPU NMI (non-maskable interrupt) exception vector.
Note: Once the HSE32 CSS is enabled and if the HSE32 clock fails, the HSE32 CSS interrupt
occurs and a NMI is automatically generated. The NMI is executed indefinitely unless the
CSSF pending bit is cleared. As a consequence, in the NMI ISR (interrupt service routine),
the user must clear the HSE CSS interrupt by setting the CSSC bit in the
interrupt clear register
If the HSE32 oscillator is used directly or indirectly as the system clock (indirectly meaning
HSE32 is used as PLL input clock and the PLL clock is used as system clock), a detected
failure causes a switch of the system clock to the MSI or the HSI16 oscillator depending on
the STOPWUCK configuration in the
the disabling of the HSE32 oscillator. If the HSE32 clock (divided or not) is the clock entry of
the PLL used as system clock when the failure occurs, the PLL is disabled too.
6.2.11 Clock security system on LSE (LSECSS)
A CSS on LSE can be activated by software writing the LSECSSON bit in the
domain control register
RTC software reset, or after a failure detection on LSE. LSECSSON must be written after
LSE and LSI are enabled (LSEON and LSION) and ready (LSERDY and LSIRDY set by
hardware), and after the RTC clock has been selected by RTCSEL. The LSI clock is
automatically enabled.The LSE must not be disabled with the LSEON bit when LSECSS is
enabled with the LSECSSON bit.
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Table 50. Clock source frequency

MSI HSI16
48 MHz 16 MHz
16 MHz 16 MHz
(RCC_CICR).
RCC clock configuration register
(RCC_BDCR). This bit can be disabled only by a hardware reset or
RM0461 Rev 5
Clock frequency
HSE32
PLLRCLK = PLLQCLK = 48 MHz
32 MHz PLLPCLK = 62 MHz
(VCO max = 344 MHz)
PLLRCLK = PLLQCLK = 16 MHz
(1)
32 MHz PLLPCLK = 21 MHz
(VCO max = 128 MHz)
RM0461
PLL
RCC clock
(RCC_CFGR), and
RCC Backup