Pwr Control Register 4 (Pwr_Cr4) - STMicroelectronics STM32WLEx Reference Manual

RM0461
5.5.4

PWR control register 4 (PWR_CR4)

This register is not reset when exiting Standby modes.
Access: additional APB cycles are needed to access this register versus those needed for a
standard APB access (three for a write and two for a read).
Address offset: 0x00C
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:12 Reserved, must be kept at reset value.
Bit 11 WRFBUSYP: Wakeup radio busy polarity
Bit 10 Reserved, must be kept at reset value.
Bit 9 VBRS: V
Bit 8 VBE: V
Bits 7:3 Reserved, must be kept at reset value.
Bit 2 WP3: Wakeup pin WKUP3 polarity
Bit 1 WP2: Wakeup pin WKUP2 polarity
Bit 0 WP1: Wakeup pin WKUP1 polarity
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. VBRS
rw rw
This bit defines the polarity used for an event detection on radio busy signal.
0: Detection on high level (rising edge)
1: Detection on low level (falling edge)
battery charging resistor selection
BAT
0: V charging through a 5 kΩ resistor
BAT
1: V charging through a 1.5 kΩ resistor
BAT
battery charging enable
BAT
0: V battery charging disabled
BAT
1: V battery charging enabled
BAT
This bit defines the polarity used for an event detection on external wake-up pin, WKUP3
0: Detection on high level (rising edge)
1: Detection on low level (falling edge)
This bit defines the polarity used for an event detection on external wake-up pin, WKUP2
0: Detection on high level (rising edge)
1: Detection on low level (falling edge)
This bit defines the polarity used for an event detection on external wake-up pin, WKUP1
0: Detection on high level (rising edge)
1: Detection on low level (falling edge)
24 23 22
Res. Res. Res.
8 7 6
VBE Res. Res.
rw
RM0461 Rev 5
Power control (PWR)
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
Res. Res. Res. WP3
rw
17 16
Res. Res.
1 0
WP2 WP1
rw rw
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