STMicroelectronics STM32WLEx Reference Manual page 39

RM0461
36.9.1
36.9.2
36.9.3
36.9.4
36.9.5
36.9.6
36.9.7
36.9.8
36.9.9
36.9.10 ITM CoreSight component identity register 0 (ITM_CIDR0) . . . . . . . 1271
36.9.11 ITM CoreSight peripheral identity register 1 (ITM_CIDR1) . . . . . . . . 1272
36.9.12 ITM CoreSight component identity register 2 (ITM_CIDR2) . . . . . . . 1272
36.9.13 ITM CoreSight component identity register 3 (ITM_CIDR3) . . . . . . . 1273
36.9.14 ITM register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1273
36.10 Trace port interface unit (TPIU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1274
36.10.1 TPIU supported port size register (TPIU_SSPSR) . . . . . . . . . . . . . . 1275
36.10.2 TPIU current port size register (TPIU_CSPSR) . . . . . . . . . . . . . . . . . 1275
36.10.3 TPIU asynchronous clock prescaler register (TPIU_ACPR) . . . . . . . 1275
36.10.4 TPIU selected pin protocol register (TPIU_SPPR) . . . . . . . . . . . . . . 1276
36.10.5 TPIU formatter and flush status register (TPIU_FFSR) . . . . . . . . . . . 1276
36.10.6 TPIU formatter and flush control register (TPIU_FFCR) . . . . . . . . . . 1277
36.10.7 TPIU formatter synchronization counter register (TPIU_FSCR) . . . . 1278
36.10.8 TPIU claim tag set register (TPIU_CLAIMSETR) . . . . . . . . . . . . . . . 1278
36.10.9 TPIU claim tag clear register (TPIU_CLAIMCLR) . . . . . . . . . . . . . . . 1279
36.10.10 TPIU device configuration register (TPIU_DEVIDR) . . . . . . . . . . . . . 1279
36.10.11 TPIU device type identifier register (TPIU_DEVTYPER) . . . . . . . . . . 1280
36.10.12 TPIU CoreSight peripheral identity register 4 (TPIU_PIDR4) . . . . . . 1280
36.10.13 TPIU CoreSight peripheral identity register 0 (TPIU_PIDR0) . . . . . . 1281
36.10.14 TPIU CoreSight peripheral identity register 1 (TPIU_PIDR1) . . . . . . 1281
36.10.15 TPIU CoreSight peripheral identity register 2 (TPIU_PIDR2) . . . . . . 1282
36.10.16 TPIU CoreSight peripheral identity register 3 (TPIU_PIDR3) . . . . . . 1282
36.10.17 TPIU CoreSight component identity register 0 (TPIU_CIDR0) . . . . . 1283
36.10.18 TPIU CoreSight peripheral identity register 1 (TPIU_CIDR1) . . . . . . 1283
36.10.19 TPIU CoreSight component identity register 2 (TPIU_CIDR2) . . . . . 1284
36.10.20 TPIU CoreSight component identity register 3 (TPIU_CIDR3) . . . . . 1284
36.10.21 TPIU register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1284
36.11 Microcontroller debug unit (DBGMCU) . . . . . . . . . . . . . . . . . . . . . . . . . 1286
ITM stimulus register x (ITM_STIMRx) . . . . . . . . . . . . . . . . . . . . . . . 1266
ITM trace enable register (ITM_TER) . . . . . . . . . . . . . . . . . . . . . . . . 1267
ITM trace privilege register (ITM_TPR) . . . . . . . . . . . . . . . . . . . . . . . 1267
ITM trace control register (ITM_TCR) . . . . . . . . . . . . . . . . . . . . . . . . 1268
ITM CoreSight peripheral identity register 4 (ITM_PIDR4) . . . . . . . . 1269
ITM CoreSight peripheral identity register 0 (ITM_PIDR0) . . . . . . . . 1269
ITM CoreSight peripheral identity register 1 (ITM_PIDR1) . . . . . . . . 1270
ITM CoreSight peripheral identity register 2 (ITM_PIDR2) . . . . . . . . 1270
ITM CoreSight peripheral identity register 3 (ITM_PIDR3) . . . . . . . . 1271
RM0461 Rev 5
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