STMicroelectronics STM32WLEx Reference Manual page 279

RM0461
6.4.24 RCC AHB3 peripheral clock enable in Sleep and Stop mode register
(RCC_AHB3SMENR)
Address offset: 0x070
Reset value: 0x0387 0000
Access: no wait state, word, half-word and byte access
31 30 29
Res. Res. Res.
15 14 13
Res. Res. Res.
Bits 31:26 Reserved, must be kept at reset value.
Bit 25 FLASHSMEN: Flash memory interface clock enable during Sleep mode.
Bit 24 SRAM2SMEN: SRAM2 memory interface clock enable during Sleep mode
Bit 23 SRAM1SMEN: SRAM1 interface clock enable during Sleep mode.
Bits 22:19 Reserved, must be kept at reset value.
Bit 18 RNGSMEN: True RNG clocks enable during Sleep and Stop modes
Bit 17 AESSMEN: AES accelerator clock enable during Sleep mode.
Bit 16 PKASMEN: PKA accelerator clock enable during Sleep mode.
Bits 15:0 Reserved, must be kept at reset value.
28 27 26 25
FLASH
Res. Res. Res.
SMEN
rw
12 11 10 9
Res. Res. Res. Res.
This bit is set and cleared by software.
0: Flash memory interface clock disabled by the clock gating during Sleep and Stop modes
1: Flash memory interface clock enabled by the clock gating during Sleep mode, disabled
during Stop mode.
This bit is set and cleared by software.
0: SRAM2 clock disabled by the clock gating during Sleep and Stop modes
1: SRAM2 clock enabled by the clock gating during Sleep mode, disabled during Stop mode.
This bit is set and cleared by software.
0: SRAM1 interface clock disabled by the clock gating during Sleep and Stop modes
1: SRAM1 interface clock enabled by the clock gating during Sleep mode, disabled during
Stop mode
This bit is set and cleared by software.
0: True RNG bus clock disabled by the clock gating during Sleep and Stop modes
1: True RNG bus clock enabled by the clock gating during Sleep mode, disabled during Stop
mode.
This bit is set and cleared by software.
0: AES clock disabled by the clock gating during Sleep and Stop modes
1: AES clock enabled by the clock gating during Sleep mode, disabled during Stop mode
This bit is set and cleared by software.
0: PKA clock disabled by the clock gating during Sleep and Stop modes
1: PKA clock enabled by the clock gating during Sleep mode, disabled during Stop mode
24 23 22
SRAM2 SRAM1
Res.
SMEN SMEN
rw rw
8 7 6
Res. Res. Res.
RM0461 Rev 5
Reset and clock control (RCC)
21 20 19 18
RNG
Res. Res. Res.
SMEN
rw
5 4 3 2
Res. Res. Res. Res.
17 16
AES PKA
SMEN SMEN
rw rw
1 0
Res. Res.
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