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Real-time clock (RTC)
30.6.20
RTC status clear register (RTC_SCR)
Address offset: 0x5C
Backup domain reset value: 0x0000 0000
System reset: not affected
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:7 Reserved, must be kept at reset value.
Bit 6 CSSRUF: Clear SSR underflow flag
Bit 5 CITSF: Clear internal timestamp flag
Bit 4 CTSOVF: Clear timestamp overflow flag
Bit 3 CTSF: Clear timestamp flag
Bit 2 CWUTF: Clear wakeup timer flag
Bit 1 CALRBF: Clear alarm B flag
Bit 0 CALRAF: Clear alarm A flag
926/1306
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
Writing '1' in this bit clears the SSRUF in the RTC_SR register.
Writing 1 in this bit clears the ITSF bit in the RTC_SR register.
Writing 1 in this bit clears the TSOVF bit in the RTC_SR register.
It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise,
an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit
is cleared.
Writing 1 in this bit clears the TSOVF bit in the RTC_SR register.
If ITSF flag is set, TSF must be cleared together with ITSF by setting CRSF and CITSF.
Writing 1 in this bit clears the WUTF bit in the RTC_SR register.
Writing 1 in this bit clears the ALRBF bit in the RTC_SR register.
Writing 1 in this bit clears the ALRAF bit in the RTC_SR register.
24
23
22
Res.
Res.
Res.
8
7
6
CSSR
CITS
Res.
Res.
UF
w
RM0461 Rev 5
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
CTSOV
CTS
CWUT
F
F
F
F
w
w
w
w
RM0461
17
16
Res.
Res.
1
0
CALRB
CALRA
F
F
w
w
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