Flash Ecc Register (Flash_Eccr) - STMicroelectronics STM32WLEx Reference Manual

RM0461
Bits 9:3 PNB[6:0]: page number selection
Bit 2 MER: mass erase
Bit 1 PER: page erase
Bit 0 PG: programming
3.8.6

FLASH ECC register (FLASH_ECCR)

Address offset: 0x018
Reset value: 0x0000 0000
Access: no wait state when no flash memory operation is ongoing. Word, half-word and byte
access.
31 30 29 28
ECCD ECCC Res. Res.
rc_w1 rc_w1
15 14 13 12
r r r r
Bit 31 ECCD: ECC detection
Bit 30 ECCC: ECC correction
Bits 29:25 Reserved, must be kept at reset value.
Bit 24 ECCCIE: ECC correction interrupt enable
Bits 23:21 Reserved, must be kept at reset value.
These bits select the 2-Kbyte page to erase.
0x00: page 0
0x01: page 1
...
0x3F: page 63
When set, this bit triggers the mass erase (all user pages).
0: page erase disabled
1: page erase enabled
0: Flash programming disabled
1: Flash programming enabled
27 26 25
Res. Res. Res. ECCCIE
11 10 9
r r r
Set by hardware when two ECC errors have been detected. When this bit is set, a NMI is
generated.
This bit is cleared by writing 1.
Set by hardware when one ECC error has been detected and corrected. An interrupt is
generated if ECCIE is set.
This bit is cleared by writing 1.
0: ECCC interrupt disabled
1: ECCC interrupt enabled
24 23 22 21
Res. Res. Res.
rw
8 7 6 5
ADDR_ECC[15:0]
r r r r
RM0461 Rev 5
Embedded flash memory (FLASH)
20 19 18
SYSF_ECC Res. Res. Res.
r
4 3 2
r r r
17 16
ADDR_ECC[16]
r
1 0
r r
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