Figure 264. Setup And Hold Timings - STMicroelectronics STM32WLEx Reference Manual

RM0461
I2C timings
The timings must be configured in order to guarantee correct data hold and setup times,
used in master and slave modes. This is done by programming the PRESC[3:0],
SCLDEL[3:0] and SDADEL[3:0] bits in the I2C_TIMINGR register.
The STM32CubeMX tool calculates and provides the I2C_TIMINGR content in the I2C
configuration window.

Figure 264. Setup and hold timings

DATA HOLD TIME
DATA HOLD TIME
SCL falling edge internal
SCL falling edge internal
detection
detection
t
t
SYNC1
SYNC1
SCL
SCL
SDA
SDA
Data hold time: in case of transmission, the data is sent on SDA output after
Data hold time: in case of transmission, the data is sent on SDA output after
the SDADEL delay, if it is already available in I2C_TXDR.
the SDADEL delay, if it is already available in I2C_TXDR.
DATA SETUP TIME
DATA SETUP TIME
SCL stretched low by the I2C
SCL stretched low by the I2C
SCL
SCL
SDA
SDA
Data setup time: in case of transmission, the SCLDEL counter starts
Data setup time: in case of transmission, the SCLDEL counter starts
when the data is sent on SDA output.
when the data is sent on SDA output.
RM0461 Rev 5
Inter-integrated circuit (I2C) interface
SDADEL: SCL stretched low by the I2C
SDADEL: SCL stretched low by the I2C
SDA output delay
SDA output delay
t
t
HD;DAT
HD;DAT
SCLDEL
SCLDEL
t
t
SU;STA
SU;DAT
MSv40108V1
MS49608V1
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