STMicroelectronics STM32WLEx Reference Manual page 152

Sub-GHz radio (SUBGHZ)
Bit Source
6
CrcErr
7 CadDone
8 CadDetected
9 Timeout
15:10 Not applicable
Cfg_DioIrq() command
Cfg_DioIrq(IrqMask, Irq1Mask, Irq2Mask, Irq3Mask) allows interrupts to be
masked and mapped on the IRQ lines.
0
Opcode
w
byte 0
bytes 2:1
bytes 4:3
bytes 6:5
bytes 8:7
Get_IrqStatus() command
Get_IrqStatus(Status, IrqStatus) returns the IRQ status.
Opcode
152/1306
Table 29. IRQ bit mapping and definition (continued)
preamble, syncword, address,
Err
CRC or length error
Channel activity detection finished
Channel activity detected
RX or TX timeout
1 2
IrqMask[15:0]
w w
bits 7:0 Opcode: 0x08
bits 15:0 IrqMask[15:0]: Global interrupt enable
See Table 29
0: IRQ disabled
1: IRQ enabled
bits 15:0 Irq1Mask[15:0]: IRQ1 line Interrupt enable
0: interrupt on IRQ1 line disable
1: interrupt on IRQ1 line enabled
bits 15:0 Irq2Mask[15:0]: IRQ2 line Interrupt enable
0: interrupt on IRQ2 line disable
1: interrupt on IRQ2 line enabled
bits 15:0 Irq3Mask[15:0]: IRQ3 line Interrupt enable
0: interrupt on IRQ3 line disable
1: interrupt on IRQ3 line enabled
0
Status[7:0]
w
Description
CRC error
Reserved
3 4
Irq1Mask[15:0]
w w
for interrupt bit map definition. For each bit:
1
r
RM0461 Rev 5
Packet type Operation
GFSK
LoRa
LoRa
LoRa
LoRa and GFSK Rx and Tx
Not applicable
5 6
Irq2Mask[15:0] Irq3Mask[15:0]
w w w
2
IrqStatus[15:0]
r
RM0461
Rx
Rx
Cad
Cad
7 8
w
3
r