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RM0461
17.7.9
DAC channel1 data output register (DAC_DOR1)
Address offset: 0x2C
Reset value: 0x0000 0000
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
Bits 31:12 Reserved, must be kept at reset value.
Bits 11:0 DACC1DOR[11:0]: DAC channel1 data output
These bits are read-only, they contain data output for DAC channel1.
17.7.10
DAC status register (DAC_SR)
Address offset: 0x34
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
CAL_
DMAU
BWST1
Res.
FLAG1
DR1
r
r
rc_w1
Bits 31:29 Reserved, must be kept at reset value.
Bit 28 Reserved, must be kept at reset value.
Bit 27 Reserved, must be kept at reset value.
Bits 26:16 Reserved, must be kept at reset value.
Bit 15 BWST1: DAC channel1 busy writing sample time flag
This bit is systematically set just after Sample and hold mode enable and is set each time the
software writes the register DAC_SHSR1, It is cleared by hardware when the write operation of
DAC_SHSR1 is complete. (It takes about 3 LSI periods of synchronization).
0:There is no write operation of DAC_SHSR1 ongoing: DAC_SHSR1 can be written
1:There is a write operation of DAC_SHSR1 ongoing: DAC_SHSR1 cannot be written
Bit 14 CAL_FLAG1: DAC channel1 calibration offset status
This bit is set and cleared by hardware
0: calibration trimming value is lower than the offset correction value
1: calibration trimming value is equal or greater than the offset correction value
27
26
25
Res.
Res.
Res.
11
10
9
r
r
r
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
24
23
22
Res.
Res.
Res.
Res.
8
7
6
DACC1DOR[11:0]
r
r
r
24
23
22
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
RM0461 Rev 5
Digital-to-analog converter (DAC)
21
20
19
18
Res.
Res.
Res.
5
4
3
2
r
r
r
r
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
Res.
Res.
Res.
Res.
17
16
Res.
Res.
1
0
r
r
17
16
Res.
Res.
1
0
Res.
Res.
507/1306
512
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