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DMA request multiplexer (DMAMUX)
12.6.5
DMAMUX request generator interrupt status register
(DMAMUX_RGSR)
Address offset: 0x140
Reset value: 0x0000 0000
This register shall be accessed at bit level by an unprivileged or privileged read, according
to the privileged mode of the considered DMAMUX request line multiplexer channel x,
depending on the privileged control bit of the connected DMA controller channel y, and
considering that the DMAMUX x channel output is connected to the y channel of the DMA
(refer to the DMAMXUX mapping implementation section).
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:4 Reserved, must be kept at reset value.
Bits 3:0 OF[3:0]: Trigger overrun event flag
The flag is set when a new trigger event occurs on DMA request generator channel x, before
the request counter underrun (the internal request counter programmed via the GNBREQ
field of the DMAMUX_RGxCR register).
The flag is cleared by writing 1 to the corresponding COFx bit in the DMAMUX_RGCFR
register.
12.6.6
DMAMUX request generator interrupt clear flag register
(DMAMUX_RGCFR)
Address offset: 0x144
Reset value: 0x0000 0000
This register shall be written at bit level by an unprivileged or privileged write, according to
the privileged mode of the considered DMAMUX request line multiplexer channel y it is
assigned to, and considering that the DMAMUX request generator x channel output is
selected by the y channel of the DMAMUX request line channel (refer to
DMAMUX_CyCR.DMAREQ_ID[7:0] and to the DMAMXUX mapping implementation
section).
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
396/1306
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
24
23
22
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
24
23
22
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
RM0461 Rev 5
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
Res.
Res.
OF3
OF2
r
r
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
Res.
Res.
COF3
COF2
w
w
RM0461
17
16
Res.
Res.
1
0
OF1
OF0
r
r
17
16
Res.
Res.
1
0
COF1
COF0
w
w
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