STMicroelectronics STM32WLEx Reference Manual page 587

RM0461
Bits 31:0 IVI[31:0]: Initialization vector input, bits [31:0]
Refer to
IVI[127:0] bitfield.
The initialization vector is only used in chaining modes other than ECB.
The AES_IVRx registers may be written only when the AES peripheral is disabled
21.7.10 AES initialization vector register 1 (AES_IVR1)
Address offset: 0x24
Reset value: 0x0000 0000
31 30 29
rw rw rw
15 14 13
rw rw rw
Bits 31:0 IVI[63:32]: Initialization vector input, bits [63:32]
Refer to the AES_IVR0 register for description of the IVI[128:0] bitfield.
21.7.11 AES initialization vector register 2 (AES_IVR2)
Address offset: 0x28
Reset value: 0x0000 0000
31 30 29
rw rw rw
15 14 13
rw rw rw
Bits 31:0 IVI[95:64]: Initialization vector input, bits [95:64]
Refer to the AES_IVR0 register for description of the IVI[128:0] bitfield.
21.7.12 AES initialization vector register 3 (AES_IVR3)
Address offset: 0x2C
Reset value: 0x0000 0000
31 30 29
rw rw rw
15 14 13
rw rw rw
Section 21.4.15: AES initialization vector registers on page 576
28 27 26 25
rw rw rw rw
12 11 10 9
rw rw rw rw
28 27 26 25
rw rw rw rw
12 11 10 9
rw rw rw rw
28 27 26 25
rw rw rw rw
12 11 10 9
rw rw rw rw
24 23 22
IVI[63:48]
rw rw rw
8 7 6
IVI[47:32]
rw rw rw
24 23 22
IVI[95:80]
rw rw rw
8 7 6
IVI[79:64]
rw rw rw
24 23 22
IVI[127:112]
rw rw rw
8 7 6
IVI[111:96]
rw rw rw
RM0461 Rev 5
AES hardware accelerator (AES)
for description of the
21 20 19 18
rw rw rw rw
5 4 3 2
rw rw rw rw
21 20 19 18
rw rw rw rw
5 4 3 2
rw rw rw rw
21 20 19 18
rw rw rw rw
5 4 3 2
rw rw rw rw
17 16
rw rw
1 0
rw rw
17 16
rw rw
1 0
rw rw
17 16
rw rw
1 0
rw rw
587/1306
591