STMicroelectronics STM32WLEx Reference Manual page 280

Reset and clock control (RCC)
6.4.25 RCC APB1 peripheral clock enable in Sleep mode register 1
(RCC_APB1SMENR1)
Address offset: 0x078
Reset value: 0xA0E2 4C01
Access: no wait state, word, half-word and byte access
31 30 29 28
LPTIM1 DAC
Res. Res.
SMEN SMEN
rw rw
15 14 13 12
SPI2S2
Res. Res. Res.
SMEN
rw
Bit 31 LPTIM1SMEN: Low power timer 1 clock enable during Sleep and Stop modes
Bit 30 Reserved, must be kept at reset value.
Bit 29 DACSMEN: DAC clock enable during Sleep and Stop modes
Bits 28:24 Reserved, must be kept at reset value.
Bit 23 I2C3SMEN: I2C3 clock enable during Sleep and Stop modes
Bit 22 I2C2SMEN: I2C2 clock enable during Sleep and Stop modes
Bit 21 I2C1SMEN: I2C1 clock enable during Sleep and Stop modes
Bits 20:18 Reserved, must be kept at reset value.
280/1306
27 26 25
Res. Res. Res.
11 10 9
RTC
WWDG
APB Res.
SMEN
SMEN
rw rw
This bit is set and cleared by software.
0: LPTIM1 bus clock disabled by the clock gating during Sleep and Stop modes
1: LPTIM1 bus clock enabled by the clock gating during Sleep mode, disabled during Stop
mode
This bit is set and cleared by software.
0: DAC clock disabled by the clock gating during Sleep and Stop modes
1: DAC clock enabled by the clock gating during Sleep mode, disabled during Stop mode
This bit is set and cleared by software.
0: I2C3 bus clock disabled by the clock gating during Sleep and Stop modes
1: I2C3 bus clock enabled by the clock gating during Sleep mode, disabled during Stop
mode
This bit is set and cleared by software.
0: I2C2 bus clock disabled by the clock gating during Sleep and Stop modes
1: I2C2 bus clock enabled by the clock gating during Sleep mode, disabled during Stop
mode
This bit is set and cleared by software.
0: I2C1 bus clock disabled by the clock gating during Sleep and Stop modes
1: I2C1 bus clock enabled by the clock gating during Sleep mode, disabled during Stop
mode
24 23 22 21
I2C3 I2C2 I2C1
Res.
SMEN SMEN SMEN
rw rw rw
8 7 6 5
Res. Res. Res. Res.
RM0461 Rev 5
20 19 18
USART2
Res. Res. Res.
4 3 2
Res. Res. Res.
RM0461
17 16
Res.
SMEN
rw
1 0
TIM2
Res.
SMEN
rw