STMicroelectronics STM32WLEx Reference Manual page 364

Direct memory access controller (DMA)
The register that contains the amount of data items to transfer is decremented after each
transfer.
A DMA channel is programmed at block transfer level.
Programmable data sizes
The transfer sizes of a single data (byte, half-word, or word) to the peripheral and memory
are programmable through, respectively, the PSIZE[1:0] and MSIZE[1:0] fields of the
DMA_CCRx register.
Pointer incrementation
The peripheral and memory pointers may be automatically incremented after each transfer,
depending on the PINC and MINC bits of the DMA_CCRx register.
If the incremented mode is enabled (PINC or MINC set to 1), the address of the next
transfer is the address of the previous one incremented by 1, 2 or 4, depending on the data
size defined in PSIZE[1:0] or MSIZE[1:0]. The first transfer address is the one programmed
in the DMA_CPARx or DMA_CMARx register. During transfers, these registers keep the
initially programmed value. The current transfer addresses (in the current internal
peripheral/memory address register) are not accessible by software.
If the channel x is configured in non-circular mode, no DMA request is served after the last
data transfer (once the number of single data to transfer reaches zero). The DMA channel
must be disabled in order to reload a new number of data items into the DMA_CNDTRx
register.
Note: If the channel x is disabled, the DMA registers are not reset. The DMA channel registers
(DMA_CCRx, DMA_CPARx and DMA_CMARx) retain the initial values programmed during
the channel configuration phase.
In circular mode, after the last data transfer, the DMA_CNDTRx register is automatically
reloaded with the initially programmed value. The current internal address registers are
reloaded with the base address values from the DMA_CPARx and DMA_CMARx registers.
Privileged / unprivileged mode
Any channel x is a privileged or unprivileged hardware resource, as configured by a
privileged software via the PRIV bit of the DMA_CCRx register.
When a channel x is configured in privileged mode, the following access controls rules are
applied:
•
An unprivileged read access to a register field of this channel is forced to return 0,
except for the privileged state of this channel x (PRIV bit of the DMA_CCRx register)
which is readable by an unprivileged software.
•
An unprivileged write access to a register field of this channel has no impact.
When a channel is configured in a privileged (or unprivileged) mode, the AHB master
transfers from the source and to the destination, are privileged (respectively unprivileged).
DMA generates a privileged bus, dma_priv[7:0], reflecting the PRIV bit of the DMA_CCRx
register, in order to keep the other hardware peripherals, like DMAMUX, informed of the
privileged / unprivileged state of each DMA channel x.
364/1306 RM0461 Rev 5
RM0461