Figure 117. Counter Timing Diagram, Internal Clock Divided By 1; Figure 118. Counter Timing Diagram, Internal Clock Divided By 2 - STMicroelectronics STM32WLEx Reference Manual

Advanced-control timer (TIM1)
Timerclock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag
Timerclock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag
624/1306

Figure 117. Counter timing diagram, internal clock divided by 1

CK_PSC
CNT_EN
31
(UIF)

Figure 118. Counter timing diagram, internal clock divided by 2

CK_PSC
CNT_EN
0034
(UIF)
RM0461 Rev 5
32 34 35 36 00
33
0036
0035
01 02
03 04 05
0000 0002
0001
RM0461
06 07
MS31078V2
0003
MS31079V2