RM0461
The high-speed external clock signal (HSE32) can be generated from the following clock
sources:
•
HSE32 external crystal
•
HSE32 external clock
–
–
The clock source must be placed as close as possible to the oscillator pins in order to
minimize output distortion and startup stabilization time.
HSE32 is controlled from the CPU and from the sub-GHz radio (see
radio
(SUBGHZ)).
HSE32 can be switched on and off using the HSEON bit in the
(RCC_CR). The HSE32 clock sources can be either an external crystal (XTAL) or an
external source including a temperature compensated crystal oscillator (TCXO). HSE32
must be enabled with the HSEON bit when used for the CPU.
The stability of the XTAL HSE32 clock may be impacted by the sub-GHz radio, depending
on the transmit output power (max +22 dBm), heating up the device. Heating depends on
the used transmit output power and the device package. Careful PCB design using thermal
heat dissipation techniques must be applied to avoid heat transfer to the HSE32 reference
clock source. For the HSE32 frequency drift requirements related to the sub-GHz radio, see
Section 4.5.1: LoRa
The HSERDY flag in the
oscillator is stable or not. At startup, the clock is not released until this bit is set by hardware.
An interrupt can be generated if enabled in the
(RCC_CIER).
The sub-GHz radio enables HSE32 autonomously for its own purpose, independently of the
HSEON bit.
Warning:
external clock source
external TCXO
modem.
RCC clock control register (RCC_CR)
The HSE32 cannot be used in LPRun mode.
RCC clock interrupt enable register
RM0461 Rev 5
Reset and clock control (RCC)
Section 4: Sub-GHz
RCC clock control register
indicates if the HSE32
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