Figure 262. I2C Block Diagram - STMicroelectronics STM32WLEx Reference Manual

RM0461
32.4.1 I2C block diagram
The block diagram of the I2C interface is shown in
i2c_ker_ck
i2c_pclk
The I2C is clocked by an independent clock source, which allows the I2C to operate
independently from the PCLK frequency.
For I2C I/Os supporting 20 mA output current drive for Fast-mode Plus operation, the driving
capability is enabled through control bits in the system configuration controller (SYSCFG).
Refer to

Figure 262. I2C block diagram

I2CCLK
Wakeup
on
address
match
PCLK
Section 32.3: I2C implementation.
Inter-integrated circuit (I2C) interface
Figure
Data control
Digital
Shift register
noise
filter
SMBUS
PEC
generation/
check
Clock control
Master clock
Digital
generation
noise
Slave clock
filter
stretching
SMBus
Timeout
check
SMBus Alert
control/status
Registers
APB bus
RM0461 Rev 5
262.
Analog
noise
GPIO
filter
logic
Analog
noise
GPIO
filter
logic
I2C_SDA
I2C_SCL
I2C_SMBA
MSv46198V2
949/1306
1014