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General-purpose I/Os (GPIO)
8.4.28
GPIOH output data register (GPIOH_ODR)
Address offset: 0x1C14
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Bits 31:4 Reserved, must be kept at reset value.
Bit 3 OD3: Port PH3 output data
This bit can be read and written by software.
Note: For atomic bit set/reset, OD bits can be individually set and/or reset by writing to the
Bits 2:0 Reserved, must be kept at reset value.
8.4.29
GPIO H bit set/reset register (GPIOH_BSRR)
Address offset: 0x1C18
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Bits 31:20 Reserved, must be kept at reset value.
Bit 19 BR3: Port PH3 reset output data bit [3] in GPIOH_ODR
Note: If both BS3 and BR3 are set, BS3 has priority.
Bits 18:4 Reserved, must be kept at reset value.
Bit 3 BS3: Port PH3 set output data bit [3] in GPIOH_ODR
Bits 2:0 Reserved, must be kept at reset value.
334/1306
28
27
26
25
Res.
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
Res.
GPIOH_BSRR and GPIOH_BRR registers.
28
27
26
25
Res.
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
Res.
This bit is read clear-write 1. A read to this bit returns the value 0.
0: No action on the corresponding GPIOH_ODR.OD3
1: Resets the corresponding GPIOH_ODR.OD3.
This bit is read clear-write 1. A read to this bit returns the value 0.
0: No action on the corresponding GPIOH_ODR.OD3
1: Sets the corresponding GPIOH_ODR.OD3.
24
23
22
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
24
23
22
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
RM0461 Rev 5
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
Res.
Res.
OD3
Res.
rw
21
20
19
18
Res.
Res.
BR3
Res.
rc_w1
5
4
3
2
Res.
Res.
BS3
Res.
rc_w1
RM0461
17
16
Res.
Res.
1
0
Res.
Res.
17
16
Res.
Res.
1
0
Res.
Res.
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