RM0461
transmission and reception modes. In transmission mode, if the data is not yet written in
I2C_TXDR when SDADEL counter is finished, the I2C keeps on stretching SCL low until the
next data is written. Then new data MSB is sent on SDA output, and SCLDEL counter starts,
continuing stretching SCL low to guarantee the data setup time.
If NOSTRETCH = 1 in slave mode, the SCL is not stretched. Consequently the SDADEL
must be programmed in such a way to guarantee also a sufficient setup time.
Table 214. I
Symbol
Parameter
t
Data hold time
HD;DAT
t
Data valid time
VD;DAT
t
Data setup time
SU;DAT
Rise time of both SDA
t
r
and SCL signals
Fall time of both SDA
t
f
and SCL signals
Additionally, in master mode, the SCL clock high and low levels must be configured by
programming the PRESC[3:0], SCLH[7:0] and SCLL[7:0] bits in the I2C_TIMINGR register.
•
When the SCL falling edge is internally detected, a delay is inserted before releasing
the SCL output.
This delay is
t
SCLL
•
When the SCL rising edge is internally detected, a delay is inserted before forcing the
SCL output to low level. This delay is
t
PRESC
Refer to
Caution:
Changing the timing configuration is not allowed when the I2C is enabled.
The I2C slave NOSTRETCH mode must also be configured before enabling the peripheral.
Refer to
Caution:
Changing the NOSTRETCH configuration is not allowed when the I2C is enabled.
2
C-SMBus specification data setup and hold times
Standard-mode
(Sm)
Min.
Max
0
-
3.45
250
-
1000
-
300
t
= (SCLL + 1) x t
SCLL
impacts the SCL low time
= (PRESC+1) x t
I2CCLK.
I2C master initialization
I2C slave initialization
Inter-integrated circuit (I2C) interface
Fast-mode
(Fm)
Min.
Max
-
0
-
-
0.9
-
100
-
-
300
-
300
where
t
PRESC
PRESC
.
t
LOW
t
= (SCLH + 1) x t
SCLH
impacts the SCL high time
t
SCLH
for more details.
for more details.
RM0461 Rev 5
Fast-mode Plus
SMBus
(Fm+)
Min.
Max
Min.
0
-
0.3
-
0.45
-
50
-
250
-
120
-
-
120
-
= (PRESC + 1) x t
I2CCLK
, where
PRESC
.
t
HIGH
Unit
Max
-
µs
-
-
1000
ns
300
.
955/1306
1014
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