Figure 238. Output Stage Of Capture/Compare Channel (Channel 1) - STMicroelectronics STM32WLEx Reference Manual

RM0461

Figure 238. Output stage of capture/compare channel (channel 1)

OC1REF
CNT>CCR1
Output
mode
CNT=CCR1
controller
OC2REF
OC1M[3:0]
TIMx_CCMR1
The capture/compare block is made of one preload register and one shadow register. Write
and read always access the preload register.
In capture mode, captures are actually done in the shadow register, which is copied into the
preload register.
In compare mode, the content of the preload register is copied into the shadow register
which is compared to the counter.
25.3.6 Input capture mode
In Input capture mode, the Capture/Compare registers (TIMx_CCRx) are used to latch the
value of the counter after a transition detected by the corresponding ICx signal. When a
capture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or
a DMA request can be sent if they are enabled. If a capture occurs while the CCxIF flag was
already high, then the over-capture flag CCxOF (TIMx_SR register) is set. CCxIF can be
cleared by software by writing it to '0' or by reading the captured data stored in the
TIMx_CCRx register. CCxOF is cleared when it is written with 0.
The following example shows how to capture the counter value in TIMx_CCR1 when TI1
input rises. To do this, use the following procedure:
1. Select the proper TI1x source (internal or external) with the TI1SEL[3:0] bits in the
TIMx_TISEL register.
2. Select the active input: TIMx_CCR1 must be linked to the TI1 input, so write the CC1S
bits to 01 in the TIMx_CCMR1 register. As soon as CC1S becomes different from 00,
the channel is configured in input and the TIMx_CCR1 register becomes read-only.
3. Program the appropriate input filter duration in relation with the signal connected to the
timer (when the input is one of the TIx (ICxF bits in the TIMx_CCMRx register). Let's
imagine that, when toggling, the input signal is not stable during at least 5 internal clock
cycles. We must program a filter duration longer than these 5 clock cycles. We can
validate a transition on TI1 when 8 consecutive samples with the new level have been
To the master mode
controller
OC1REFC
Dead-time
Output
selector generator
DTG[7:0]
TIMx_BDTR
RM0461 Rev 5
General-purpose timers (TIM16/TIM17)
'0'
x0
01
OC1_DT
11
TIM1_CCER
OC1N_DT
11
10
'0'
0x
CC1NE CC1E
TIMx_CCER
TIMx_CCER
0
Output
enable
1
circuit
CC1P
0
Output
OC1N
enable
1
circuit
CC1E TIMx_CCER
CC1NE
MOE OSSI OSSR
CC1NP
TIMx_BDTR
OIS1 OIS1N TIMx_CR2
OC1
MSv65226V1
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