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Reset and clock control (RCC)
Bit 13 Reserved, must be kept at reset value.
Bit 12 SPI1EN: SPI1 clock enable
This bit is set and cleared by software.
0: SPI1 clock disabled
1: SPI1 clock enabled
Bit 11 TIM1EN: TIM1 timer clock enable
This bit is set and cleared by software.
0: TIM1 timer clock disabled
1: TIM1P timer clock enabled
Bit 10 Reserved, must be kept at reset value.
Bit 9 ADCEN: ADC clocks enable
This bit is set and cleared by software.
0: ADC bus and kernel clocks disabled
1: ADC bus and kernel clocks enabled
Bits 8:0 Reserved, must be kept at reset value.
6.4.21
RCC APB3 peripheral clock enable register (RCC_APB3ENR)
Address offset: 0x64
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
Note:
When the peripheral clock is not active, the peripheral registers read or write access is not
supported.
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:1 Reserved, must be kept at reset value.
Bit 0 SUBGHZSPIEN: sub-GHz radio SPI clock enable
276/1306
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
This bit is set and cleared by software.
0: Sub-GHz radio SPI clock disable
1: Sub-GHz radio SPI clock enable
24
23
22
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
RM0461 Rev 5
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
Res.
Res.
Res.
Res.
RM0461
17
16
Res.
Res.
1
0
Res.
rw
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