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Low-power timer (LPTIM)
26.7.12
LPTIM repetition register (LPTIM_RCR)
Address offset: 0x028
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 REP[7:0]: Repetition register value
REP is the repetition value for the LPTIM.
Caution:
The LPTIM_RCR register must only be modified when the LPTIM is enabled (ENABLE bit
set to '1'). When using repetition counter with PRELOAD = 0, LPTIM_RCR register must be
changed at least five counter cycles before the auto reload match event, otherwise an
unpredictable behavior may occur.
868/1306
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
24
23
22
Res.
Res.
Res.
8
7
6
Res.
rw
rw
RM0461 Rev 5
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
REP[7:0]
rw
rw
rw
rw
RM0461
17
16
Res.
Res.
1
0
rw
rw
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