STMicroelectronics STM32WLEx Reference Manual page 250

Reset and clock control (RCC)
domain is ongoing, Stop, Standby and Shutdown modes entry is delayed until the APB
access is finished.
6.4 RCC registers
6.4.1 RCC clock control register (RCC_CR)
Address offset: 0x000
Reset value: 0x0000 0061
Access: no wait state, word, half-word and byte access
31 30 29
Res. Res. Res. Res.
15 14 13
HSI
Res. Res. Res.
KERDY
Bits 31:26 Reserved, must be kept at reset value.
Bit 25 PLLRDY: Main PLL clock ready flag
This bit is set by hardware to indicate that the main PLL is locked.
0: PLL unlocked
1: PLL locked
Bit 24 PLLON: Main PLL enable
This bit is set and cleared by software to enable the main PLL. It is also cleared by hardware
when entering Stop, Standby or Shutdown mode. This bit cannot be reset if the main PLL
clock is used as the system clock.
0: Main PLL off
1: Main PLL on
Bits 23:22 Reserved, must be kept at reset value.
Bit 21 HSEBYPPWR: HSE32 VDDTCXO output on package pin PB0-VDDTCXO enable
This bit is set and cleared by software to control the function on package pin
PB0-VDDTCXO. It can only be written when HSE32 oscillator is disabled
(HSEON = HSERDY = 0).
0: PB0 selected
1: VDDTCXO selected
Bit 20 HSEPRE: HSE32 SYSCLK prescaler
This bit is set and cleared by software to control the division factor of SYSCLK when
selecting HSE32 clock.
0: SYSCLK not divided (HSE32)
1: SYSCLK divided by two (HSE32 / 2)
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28 27 26 25
PLL
Res. Res.
RDY
r
12 11 10 9
HSI HSI HSI
ASFS RDY KERON
r rw r rw
24 23 22
HSEBY
PLLON Res. Res.
PPWR
rw
8 7 6
HSION MSIRANGE[3:0]
rw rw rw
RM0461 Rev 5
21 20 19 18
HSE CSS
Res.
PRE ON
rw rw rs
5 4 3 2
MSIRG MSI
SEL PLLEN
rw rw rs rw
RM0461
17 16
HSE
HSEON
RDY
r rw
1 0
MSI
MSION
RDY
r rw