Table of Contents
Advertisement
Reset and clock control (RCC)
6.4.15
RCC AHB1 peripheral clock enable register (RCC_AHB1ENR)
Address offset: 0x048
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
Note:
When the peripheral clock is not active, the peripheral registers read or write access is not
supported.
31
30
29
Res.
Res.
Res.
Res.
15
14
13
CRC
Res.
Res.
Res.
Bits 31:13 Reserved, must be kept at reset value.
Bit 12 CRCEN: CRC clock enable
Bits 11:3 Reserved, must be kept at reset value.
Bit 2 DMAMUX1EN: DMAMUX1 clock enable
Bit 1 DMA2EN: DMA2 clock enable
Bit 0 DMA1EN: DMA1 clock enable
270/1306
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
EN
rw
This bit is set and cleared by software.
0: CRC clock disabled
1: CRC clock enabled
This bit is set and cleared by software.
0: DMAMUX1 clock disabled
1: DMAMUX1 clock enabled
This bit is set and cleared by software.
0: DMA2 clock disabled
1: DMA2 clock enabled
This bit is set and cleared by software.
0: DMA1 clock disabled
1: DMA1 clock enabled
24
23
22
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
RM0461 Rev 5
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
DMA
Res.
Res.
Res.
MUX1
EN
rw
RM0461
17
16
Res.
Res.
1
0
DMA2
DMA1
EN
EN
rw
rw
Advertisement
Chapters
Table of Contents
Need help?
Do you have a question about the STM32WLEx and is the answer not in the manual?