STMicroelectronics STM32WLEx Reference Manual page 375

RM0461
Bits 31:21 Reserved, must be kept at reset value.
Bit 20 PRIV: privileged mode
This bit can only be set and cleared by a privileged software.
0: disabled
1: enabled
This bit must not be written when the channel is enabled (EN = 1).
It is read-only when the channel is enabled (EN = 1).
Bits 19:15 Reserved, must be kept at reset value.
Bit 14 MEM2MEM: memory-to-memory mode
0: disabled
1: enabled
Note: This bit is set and cleared by software (privileged software if the channel is in privileged
Bits 13:12 PL[1:0]: priority level
00: low
01: medium
10: high
11: very high
Note: This field is set and cleared by software (privileged software if the channel is in
Bits 11:10 MSIZE[1:0]: memory size
Defines the data size of each DMA transfer to the identified memory.
In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the
memory destination if DIR = 0.
In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the
peripheral destination if DIR = 0.
00: 8 bits
01: 16 bits
10: 32 bits
11: reserved
Note: This field is set and cleared by software (privileged software if the channel is in
mode).
It must not be written when the channel is enabled (EN = 1).
It is read-only when the channel is enabled (EN = 1).
privileged mode).
It must not be written when the channel is enabled (EN = 1).
It is read-only when the channel is enabled (EN = 1).
privileged mode).
It must not be written when the channel is enabled (EN = 1).
It is read-only when the channel is enabled (EN = 1).
RM0461 Rev 5
Direct memory access controller (DMA)
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