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RM0461
Bit 17 USART2SMEN: USART2 clock enable during Sleep and Stop modes
Bits 16:15 Reserved, must be kept at reset value.
Bit 14 SPI2S2SMEN: SPI2S2 clock enable during Sleep and Stop modes
Bits 13:12 Reserved, must be kept at reset value.
Bit 11 WWDGSMEN: Window watchdog clocks enable during Sleep and Stop modes
Bit 10 RTCAPBSMEN: RTC APB bus clock enable during Sleep and Stop modes
Bits 9:1 Reserved, must be kept at reset value.
Bit 0 TIM2SMEN: Timer 2 clock enable during Sleep and Stop modes
6.4.26
RCC APB1 peripheral clock enable in Sleep mode register 2
(RCC_APB1SMENR2)
Address offset: 0x07C
Reset value: 0x0000 0061
Access: no wait state, word, half-word and byte access
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
This bit is set and cleared by software.
0: USART2 bus clock disabled by the clock gating during Sleep and Stop modes
1: USART2 bus clock enabled by the clock gating during Sleep mode, disabled during Stop
mode
This bit is set and cleared by software.
0: SPI2S2 clock disabled by the clock gating during Sleep and Stop modes
1: SPI2S2 clock enabled by the clock gating during Sleep mode, disabled during Stop mode
This bit is set and cleared by software.It is forced to 1 by hardware when the hardware
WWDG_SW option is reset.
0: Window watchdog clock disabled by the clock gating during Sleep and Stop modes
1: Window watchdog clocks enabled by the clock gating during Sleep mode, disabled during
Stop mode
This bit is set and cleared by software. RTC kernel clock is controlled by the RTCEN bit in
the RCC_BDCR register.
0: RTC APB bus clock disabled during by the clock gating during Sleep and Stop modes
1: RTC APB bus clock enabled during by the clock gating during Sleep mode, disabled
during Stop mode
This bit is set and cleared by software.
0: TIM2 clock disabled by the clock gating during Sleep and Stop modes
1: TIM2 clock enabled by the clock gating during Sleep mode, disabled during Stop mode
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
24
23
22
Res.
Res.
Res.
Res.
8
7
6
Res.
Res.
rw
RM0461 Rev 5
Reset and clock control (RCC)
21
20
19
18
Res.
Res.
Res.
5
4
3
2
Res.
Res.
Res.
rw
17
16
Res.
Res.
1
0
Res.
rw
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