STMicroelectronics STM32WLEx Reference Manual page 257

RM0461
Bits 1:0 SW[1:0]: System clock switch
6.4.4 RCC PLL configuration register (RCC_PLLCFGR)
Address offset: 0x00C
Reset value: 0x2204 0100
Access: no wait state, word, half-word and byte access
This register is used to configure the main PLL clock outputs according to the formulas:
• f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
• f(PLL_P) = f(VCO clock) / PLLP
• f(PLL_Q) = f(VCO clock) / PLLQ
• f(PLL_R) = f(VCO clock) / PLLR
31 30 29
PLL
PLLR[2:0]
REN
rw rw rw
15 14 13
Res.
rw rw
Bits 31:29 PLLR[2:0]: Main PLL division factor for PLLRCLK
Note: The software must set these bits correctly not to exceed 48 MHz on this domain in
These bits are set and cleared by software to select system clock source (SYSCLK). They
are configured by hardware to force MSI oscillator selection when exiting Shutdown mode
and Standby mode.
These bits can also be configured by hardware to force MSI or HSI16 oscillator selection
when exiting Stop mode or in case of failure of the HSE32 oscillator, depending on
STOPWUCK value.
00: MSI selected as system clock
01: HSI16 selected as system clock
10: HSE32 selected as system clock
11: PLLRCLK selected as system clock
28 27 26 25
PLLQ[2:0]
rw rw rw rw
12 11 10 9
PLLN[6:0]
rw rw rw rw
These bits are set and cleared by software to control the frequency of the main PLL output
clock PLLRCLK. This output can be selected as system clock. These bits can be written only
if PLL is disabled.
PLLRCLK output clock frequency = VCO frequency / PLLR with PLLR = 2, 3, 4,... or 8 [VCO
frequency / (N + 1)]
000: reserved
001: PLLR = 2
010: PLLR = 3
011: PLLR = 4
100: PLLR = 5
101: PLLR = 6
110: PLLR = 7
111: PLLR = 8
range 1.
24 23 22
PLL
Res. Res.
QEN
rw
8 7 6
Res. PLLM[2:0]
rw rw
RM0461 Rev 5
Reset and clock control (RCC)
21 20 19 18
PLLP[4:0]
rw rw rw rw
5 4 3 2
Res. Res.
rw rw
17 16
PLL
PEN
rw rw
1 0
PLLSRC[1:0]
rw rw
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