STMicroelectronics STM32WLEx Reference Manual page 216

Power control (PWR)
Bit 11 EWRFBUSY: radio busy wakeup from Standby for CPU enable
Bit 10 APC: Apply pull-up and pull-down configuration from CPU
Bit 9 RRS: SRAM2 retention in Standby mode
Bit 8 EWPVD: PVD and wakeup for CPU enable (when sub-GHz radio in active state)
Bit 7 ULPEN: Ultra-low-power enable
Caution: When enabled and if the supply voltage drops below the minimum operating
Bits 6:3 Reserved, must be kept at reset value.
Bit 2 EWUP3: wakeup pin WKUP3 for CPUenable
Bit 1 EWUP2: wakeup pin WKUP2 for CPUenable
Bit 0 EWUP1: wakeup pin WKUP1 for CPU enable
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When this bit is set, the radio busy is enabled and triggers a wakeup from Standby event to
CPUwhen a rising or a falling edge occurs. The active edge is configured via the
WRFBUSYP bit in the PWR control register 4
When this bit is set, the I/O pull-up and pull-down configurations defined in the PWR_PUCRx
and PWR_PDCRx registers are applied. When this bit is cleared, the PWR_PUCRx and
PWR_PDCRx registers are not applied to the I/Os.
0: SRAM2 powered off in Standby mode (SRAM2 content lost)
1: SRAM2 powered by the low-power regulator in Standby mode (SRAM2 content kept)
This bit is set and reset by software.
When this bit is set, the PVD is enabled while the sub-GHz radio is active and triggers an
interrupt and wakeup from Stop, Standby event to CPU, when the voltage level drops below
the PVD threshold level.
0: PVD not enabled by the sub-GHz radio active state
1: PVD enabled while the sub-GHz radio is active
Enable/disable periodical sampling of supply voltage in Stop and Standby modes for
detecting condition of PDR and BOR reset.
0: Disable (the supply voltage is monitored continuously)
1: Enable, when set, the supply voltage is sampled for PDR/BOR reset condition only
periodically and not continuously, in order to save power. The sampling period is typically
12 ms, but is strongly linked to the temperature (the period decreases when the temperature
increases).
condition between two supply voltage samples, the reset condition is missed and no
reset is generated.
When this bit is set, the external wakeup pin WKUP3 is enabled and triggers an interrupt and
wakeup from Stop, Standby or Shutdown event when a rising or a falling edge occurs to
CPU. The active edge is configured via the WP3 bit in the
(PWR_CR4).
When this bit is set, the external wakeup pin WKUP2 is enabled and triggers an interrupt and
wakeup from Stop, Standby or Shutdown event when a rising or a falling edge occurs to
CPU. The active edge is configured via the WP2 bit in the
(PWR_CR4).
When this bit is set, the external wakeup pin WKUP1 is enabled and triggers an interrupt and
wakeup from Stop, Standby or Shutdown event when a rising or a falling edge occurs to
CPU. The active edge is configured via the WP1 bit in the
(PWR_CR4).
(PWR_CR4).
RM0461 Rev 5
PWR control register 4
PWR control register 4
PWR control register 4
RM0461