STMicroelectronics STM32WLEx Reference Manual page 329

RM0461
8.4.19 GPIOC configuration lock register (GPIOC_LCKR)
Address offset: 0x081C
Reset value: 0x0000 0000
This register is used to lock the configuration of the port bits when a correct write sequence
is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the
GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the lock
sequence has been applied on a port bit, the value of this port bit can no longer be modified
until the next MCU reset or peripheral reset.
Note: A specific write sequence is used to write to the GPIOC_LCKR register. Only word access
(32-bit long) is allowed during this locking sequence.
Each lock bit freezes a specific configuration register (control and alternate function
registers).
31 30 29
Res. Res. Res.
15 14 13
LCK15 LCK14 LCK13
rw rw rw
Bits 31:17 Reserved, must be kept at reset value.
Bit 16 LCKK: Lock key
Note: During the LOCK key write sequence, the value of LCK[15:0] must not change.
Bits 15:13 LCKy: Port PCy lock configuration (y = 15 to 13)
Bits 12:7 Reserved, must be kept at reset value.
Bits 6:0 LCKy: Port PCy lock configuration (y = 6 to 0)
28 27 26 25
Res. Res. Res. Res.
12 11 10 9
Res. Res. Res. Res.
This bit can be read any time. It can only be modified using the lock key write sequence.
0: Port PC configuration lock key not active
1: Port PC configuration lock key active. GPIOC_LCKR is locked until the next MCU reset or
peripheral reset.
LOCK key write sequence:
WR LCKR[16] = 1 + LCKR[15:0]
WR LCKR[16] = 0 + LCKR[15:0]
WR LCKR[16] = 1 + LCKR[15:0]
RD LCKR
RD LCKR[16] = 1 (This read operation is optional but it confirms that the lock is active.)
Any error in the lock sequence aborts the lock.
After the first lock sequence on any bit of the port, any read access on the LCKK bit
returns 1 until the next MCU reset or peripheral reset.
This bit is read/write but can only be written when the LCKK bit is 0.
0: Port PCy configuration not locked
1: Port PCy configuration locked
24 23 22
Res. Res. Res.
8 7 6
Res. Res. LCK6
rw
RM0461 Rev 5
General-purpose I/Os (GPIO)
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
LCK5 LCK4 LCK3 LCK2
rw rw rw rw
17 16
Res. LCKK
rw
1 0
LCK1 LCK0
rw rw
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