STMicroelectronics STM32WLEx Reference Manual page 273

RM0461
6.4.18 RCC APB1 peripheral clock enable register 1 (RCC_APB1ENR1)
Address offset: 0x058
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
Note: When the peripheral clock is not active, the peripheral registers read or write access is not
supported.
31 30 29 28
LPTIM1 DAC
Res. Res.
EN EN
rw rw
15 14 13 12
SPI2S2
Res. Res. Res.
EN
rw
Bit 31 LPTIM1EN: Low power timer 1 clocks enable
Bit 30 Reserved, must be kept at reset value.
Bit 29 DACEN: DAC clock enable
Bits 28:24 Reserved, must be kept at reset value.
Bit 23 I2C3EN: I2C3 clocks enable
Bit 22 I2C2EN: I2C2 clocks enable
Bit 21 I2C1EN: I2C1 clocks enable
Bits 20:18 Reserved, must be kept at reset value.
Bit 17 USART2EN: USART2 clock enable
Bits 16:15 Reserved, must be kept at reset value.
27 26 25
Res. Res. Res.
11 10 9
WWDG
Res.
EN
rs rw
This bit is set and cleared by software.
0: LPTIM1 bus and kernel clocks disabled
1: LPTIM1 bus and kernel clocks enabled
This bit is set and cleared by software.
0: DAC clock disabled
1: DAC clock enabled
This bit is set and cleared by software.
0: I2C3 bus and kernel clocks disabled
1: I2C3 bus and kernel clocks enabled
This bit is set and cleared by software.
0: I2C2 bus and kernel clocks disabled
1: I2C2 bus and kernel clocks enabled
This bit is set and cleared by software.
0: I2C1 bus and kernel clocks disabled
1: I2C1 bus and kernel clocks enabled
This bit is set and cleared by software.
0: USART2 bus and kernel clocks disabled
1: USART2 bus and kernel clocks enabled
24 23 22 21
I2C3 I2C2 I2C1
Res.
EN EN EN
rw rw rw
8 7 6 5
Res. Res. Res. Res.
RM0461 Rev 5
Reset and clock control (RCC)
20 19 18
USART2
Res. Res. Res.
4 3 2
Res. Res. Res.
17 16
Res.
EN
rw
1 0
TIM2
Res.
EN
rw
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