Sub-Ghz Radio Frame Limit Lsb Register (Subghz_Ram_Frameliml); Sub-Ghz Radio Generic Bit Synchronization Register (Subghz_Gbsyncr); Sub-Ghz Radio Generic Cfo Msb Register (Subghz_Gcforh) - STMicroelectronics STM32WLEx Reference Manual

RM0461
4.10.6 Sub-GHz radio frame limit LSB register
(SUBGHZ_RAM_FRAMELIML)
Address offset: 0x0F5
Reset value: 0x00
7 6
rw rw
Bits 7:0 FRAMELIML[7:0]: frame limit LSB bits
4.10.7 Sub-GHz radio generic bit synchronization register
(SUBGHZ_GBSYNCR)
Address offset: 0x6AC
Reset value: 0x00
This register must be cleared to 0x00 when using packet types other than LoRa.
7 6
Res. SBITSYNCEN
rw
Bit 7 Reserved, must be kept at reset value.
Bit 6 SBITSYNCEN: LoRa simple bit synchronization enable
Bit 5 RXDINV: LoRa receive data inversion
Bit 4 BITSYNCDIS: LoRa normal bit synchronization enable
Bits 3:0 Reserved, must be kept at reset value.
4.10.8

Sub-GHz radio generic CFO MSB register (SUBGHZ_GCFORH)

Address offset: 0x6B0
Reset value: 0x00
7 6
Res Res
5
rw
5
RXDINV BITSYNCDIS
rw
This bit must be cleared to 0 when using generic packet and BPSK type.
0: simple bit synchronization disabled
1: simple bit synchronization enabled
This bit must be cleared to 0 when using generic packet and BPSK type.
0: receive data not inverted
1: receive data inverted
This bit must be cleared to 0 when using generic packet and BPSK type.
0: normal bit synchronization enabled
1: normal bit synchronization disabled
5
Res
4 3
FRAMELIML[7:0]
rw rw
4 3
Res.
rw
4 3
Res
r
RM0461 Rev 5
Sub-GHz radio (SUBGHZ)
2 1
rw rw
2 1
Res. Res.
2 1
DEMOD_CFO[3:0]
r r
0
rw
0
Res.
0
r
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