Figure 119. Counter Timing Diagram, Internal Clock Divided By 4; Figure 120. Counter Timing Diagram, Internal Clock Divided By N - STMicroelectronics STM32WLEx Reference Manual

RM0461 Advanced-control timer (TIM1)

Figure 119. Counter timing diagram, internal clock divided by 4

CK_PSC
CNT_EN
Timerclock = CK_CNT
Counter register
0035 0036 0000 0001
Counter overflow
Update event (UEV)
Update interrupt flag
(UIF)
MS31080V2

Figure 120. Counter timing diagram, internal clock divided by N

CK_PSC
Timerclock = CK_CNT
1F 00
Counter register 20
Counter overflow
Update event (UEV)
Update interrupt flag
(UIF)
MS31081V2
RM0461 Rev 5 625/1306
718