Table 12. Rdp Regression From Level 1 To Level 0 And Memory Erase - STMicroelectronics STM32WLEx Reference Manual

RM0461
Level 2: no debug
In this level, the protection level 1 is guaranteed. In addition, the CPU debug port, the boot
from RAM (boot RAM mode) and the boot from system memory (bootloader mode) are no
more available. In user execution mode (boot FLASH mode), all operations are allowed on
the main flash memory. On the contrary, only read and secure write operations can be
performed on the option bytes.
Note: The debug feature is also disabled under reset.
STMicroelectronics is not able to perform analysis on defective parts on which the level 2
protection has been set.
Change the readout protection level
It is easy to move from level 0 to level 1 by changing the value of the RDP byte to any value
(except 0xCC). By programming the 0xCC value in the RDP byte, it is possible to go to
level 2 directly from level 0 or from level 1. Once in level 2 it is no more possible to modify
the readout protection level.
When the RDP is reprogrammed to the value 0xAA to move from level 1 to level 0, a mass
erase of the main flash memory is performed if PCROP_RDP is set in
FLASH_PCROP1AER. Backup registers (RTC_BKPxR in the RTC), SRAM1, SRAM2 and
PKA SRAM are also erased. The user options except PCROP protection are set to their
previous values copied from FLASH_OPTR, FLASH_WRP1xR (x= A or B). PCROP is
disabled. The OTP area is not affected by mass erase and remains unchanged.
If the bit PCROP_RDP is cleared in FLASH_PCROP1AER, the full mass erase is replaced
by a partial mass erase that is successive page erases, except for the pages protected by
PCROP. This is done in order to keep the PCROP code. Only when the flash memory is
erased, options are re-programmed with their previous values. This is also true for
FLASH_PCROP1xSR and FLASH_PCROP1xER registers (x= A or B).

Table 12. RDP regression from level 1 to level 0 and memory erase

PCROP PCROP_RDP
None
Partial
Complete
Note: Full mass erase or partial mass erase is performed only when level 1 is active and level 0 is
requested. When the protection level is increased (0→1, 1→2, 0→2), there is no mass
erase.
To validate the protection level change, the option bytes must be reloaded through the
OBL_LAUNCH bit in FLASH_CR, or a POR, or wakeup from Standby or Shutdown mode.
x
Flash, SRAM1, SRAM2, PKA SRAM and backup registers mass erase
1
Flash multiple page erase of all non-PCROP pages
SRAM1, SRAM2, PKA SRAM and backup registers erased (PCROP Flash pages
conserved)
0
Flash, SRAM1, SRAM2 and backup registers conserved
PKA SRAM erase.
Comment
RM0461 Rev 5
Embedded flash memory (FLASH)
87/1306
108