Functional Description - Holtek HT49RU80 Manual

Functional Description

Execution Flow
The system clock is derived from either a crystal or an
RC oscillator or a 32768Hz crystal oscillator. It is inter-
nally divided into four non-overlapping clocks. One in-
struction cycle consists of four system clock cycles.
Instruction fetching and execution are pipelined in such
a way that a fetch takes one instruction cycle while de-
coding and execution takes the next instruction cycle.
The pipelining scheme makes it possible for each in-
struction to be effectively executed in a cycle. If an in-
struction changes the value of the program counter, two
cycles are required to complete the instruction.
Program Counter - PC
The program counter (PC) is 14 bits wide and controls
the sequence in which the instructions stored in the pro-
gram ROM are executed. The contents of the PC can
Mode
Initial Reset
External Interrupt 0
External Interrupt 1
Timer/Event Counter 0 Overflow
Timer/Event Counter 1 Overflow
UART Interrupt
Multi Function Interrupt
Skip
Loading PCL
Jump, Call Branch
Return from Subroutine
Note: *13~*0: Program counter bits
#12~#0: Instruction code bits
P r o g r a m C o u n t e r
B a n k P o i n t e r ( B P )
Rev. 1.10
specify a maximum of 16384 addresses.
After accessing a program memory word to fetch an in-
struction code, the value of the PC is incremented by
²1². The PC then points to the memory word containing
the next instruction code.
When executing a jump instruction, a conditional skip
execution, loading a PCL register, a subroutine call, an
initial reset, an internal interrupt, an external interrupt, or
returning from a subroutine, the PC manages the pro-
gram transfer by loading the address corresponding to
each instruction.
The conditional skip is activated by instructions. Once
the condition is met, the next instruction, fetched during
the current instruction execution, is discarded and a
dummy cycle replaces it to get a proper instruction; oth-
erwise the program proceeds to the next instruction.
Execution Flow
*13 *12~*8 *7
0 00000 0
0 00000 0
0 00000 0
0 00000 0
0 00000 0
0 00000 0
0 00000 0
Program Counter + 2 (within the current bank)
*13 *12~*8 @7
BP.5 #12~#8 #7
S13 S12~S8 S7
Program Counter
S13~S0: Stack register bits
@7~@0: PCL bits
7
HT49RU80/HT49CU80
Program Counter
*6 *5 *4 *3
0 0 0 0
0 0 0 0
0 0 0 1
0 0 0 1
0 0 1 0
0 0 1 0
0 0 1 1
@6 @5 @4 @3
#6 #5 #4 #3
S6 S5 S4 S3
*2 *1 *0
0 0 0
1 0 0
0 0 0
1 0 0
0 0 0
1 0 0
0 0 0
@2 @1 @0
#2 #1 #0
S2 S1 S0
March 2, 2007