Functional Description - Holtek HT827A0 Manual

Functional Description

Executive flow
The HT827A0 provides a system clock which is
derived from a crystal or an RC type of oscillator.
The clock is internally divided into four
non-overlapping clocks denoted by P1, P2, P3 and
P4. An instruction cycle consists of T1~T4.
Instruction fetching and execution are
pipelined in such a way that a fetch takes an in-
struction cycle while decoding and execution
take the next instruction cycle. The pipelining
scheme causes each instruction to execute ef-
fectively in a cycle. If an instruction changes
the program counter, two cycles are required to
complete that instruction.
Program counter - PC
The program counter (PC) controls the se-
quence in which the instructions stored in the
program ROM are executed.
The contents of the program counter are incre-
mented by one after a program memory word is
accessed to fetch an instruction code. The pro-
T 1
S y s t e m C l o c k
O S C 2 ( R C o n l y )
P 1
P 2
P 3
P 4
P C
F e t c h I N S T ( P C )
E x e c u t e I N S T ( P C - 1 )
gram counter then points to a memory word
containing the next instruction code.
The PC manipulates a program transfer by
loading the address corresponding to each in-
struction when executing a jump instruction,
conditional skip execution, loading PCL regis-
ter, subroutine call, initial reset, internal inter-
rupt, external interrupt or return from
subroutine.
The conditional skip is activated by instructions.
Once the condition is satisfied, the next instruc-
tion, fetched during the current instruction exe-
cution, is discarded and a dummy cycle replaces
it to get a proper instruction. Otherwise, the sys-
tem will proceed with the next instructions.
The lower byte of the program counter (PCL) is
a readable and writable register (06H). Moving
data into PCL performs a short jump. The desti-
nation is within 256 locations.
Once a control transfer takes place, the execu-
tion suffers from an additional dummy cycle.
T 2 T 3 T 4 T 1 T 2 T 3
P C P C + 1
F e t c h I N S T ( P C + 1 )
E x e c u t e I N S T ( P C )
Execution flow
8
HT827A0
T 4 T 1 T 2 T 3 T 4
I n t e r n a l
P h a s e
C l o c k s
P C + 2
F e t c h I N S T ( P C + 2 )
E x e c u t e I N S T ( P C + 1 )
March 15, 2000