Timer Counter Register - Ctr - Holtek HT32F12345 User Manual

32-Bit Arm ® Cortex ® -M3 MCU
HT32F12345
Timer Counter Register – CTR
This register specifies the timer enable bit (TME), CRR buffer enable bit (CRBE) and Channel PDMA selection
bit (CHCCDS).
Offset: 0x010
Reset value: 0x0000_0000
31
Type/Reset
23
Type/Reset
15
Type/Reset
7
Type/Reset
Bits Field
[16] CHCCDS
[1] CRBE
[0] TME
Rev. 1.10
30 29 28
22 21 20
Reserved
14 13 12
6 5 4
Reserved
Descriptions
Channel PDMA event selection
0: Send CHx PDMA request when channel capture / compare event occurs
1: Send CHx PDMA request when Update event occurs
Counter-Reload register Buffer Enable
0: Counter reload register can be updated immediately
1: Counter reload register can not be updated until the update event occurs
Timer Enable bit
0: GPTM off
1: GPTM on – GPTM functions normally
When the TME bit is cleared to 0, the counter is stopped and the GPTM consumes
no power in any operation mode except for the single pulse mode and the slave
trigger mode. In these two modes the TME bit can automatically be set to 1 by
hardware which permits all the GPTM registers to function normally.
257 of 590
27 26
Reserved
19 18
11 10
Reserved
3 2
CRBE
RW
25 24
17 16
CHCCDS
RW 0
9 8
1 0
TME
0 RW 0
November 28, 2018